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APPLICATION NOTE

REJ05B0466-0100Z/Rev.1.00 May 2004 Page 1 of 6

M16C/6N Group

Differences between M16C/6NA and M16C/6N4

1. Abstract

This document describes the differences between M16C/6NA and M16C/6N4 groups.

2. Introduction

The explanation of this document is applied to the following condition:

Applicable MCU: M16C/6NA, M16C/6N4

3. Contents

3.1 Function differences

Table 3.1.1 and table 3.1.2 show the function differences (mask ROM version and flash memory

version). Table 3.1.3 shows the function differences (flash memory version).

Table 3.1.1 Function differences (mask ROM version and flash memory version)-1(Note1)

Item M16C/6NA M16C/6N4

Shortest instruction execution

time

62.5ns(f(X

)=16MHz, V

=4.2 to 5.5V) 50ns(f(BCLK)=20MHz, V

=4.0 to 5.5V)

Clock generating circuit

, X

CIN

, on-chip oscillator

When placed in low power mode, the

divided-n value for the main clock does

not change.

PLL, X

, X

CIN

, on-chip oscillator

When placed in low power mode, a

divided-8 value is used for these clocks.

The X

drive capability is set to HIGH.

Low power consumption

60mA

=5V, f(X

)=16MHz without software

wait, mask version)

18mA

=5V, f(BCLK)=20MHz, 1/1

prescaler, without software wait, mask

version)

Internal reserved

area (Note 2)

Depend on the mode

M16C/6NA's internal reserved area +

27000

to 27FFF

Memory

expansion

mode and

microproces

sor mode

Address bus and

I/O port

P4_0 to P4_3:

Switchable between address bus and

I/O port

P4_0 to P4_3, P3_4 to P3_7:

Switchable between address bus and

I/O port

Access to SFR 1 wait fixed Variable (1 to 2 waits)

Software wait to external area Variable (0 to 2 wait) Variable (0 to 3 waits)

Protected by the

PRC0bit

CM0, CM1, CM2, PCLKR, CCLKR

CM0, CM1, CM2, PLC0, PCLKR,

CCLKR

Protected by the

PRC1bit

PM0, PM1

PM0, PM1, PM2, TB2SC, INVC0,

INVC1

Protect

(PRCR

Protected by the

PRC2bit

PD7, PD9, S3C PD7, PD9, S3C

Watchdog timer

Watchdog timer interrupt

No count source protective mode

Watchdog timer interrupt or watchdog

timer reset is selected

Count source protective mode is

available

Address match interrupt 2 4

Note1: For details and characteristics, refer to hardware manual. When switching to M16C/6N4 group, conduct the equivalent of system

evaluation tests conducted in M16C/6NA group.

Note2: The PM1 register's PM13 bit differs in the value after reset.

1 2 3 4 5 6

M16C/6N Group 1
DEVISION HISTORY 5

Inhaltsverzeichnis

Seite 1 - M16C/6N Group

APPLICATION NOTEREJ05B0466-0100Z/Rev.1.00 May 2004 Page 1 of 6M16C/6N GroupDifferences between M16C/6NA and M16C/6N4 1. AbstractThis document describ

Seite 2

M16C/6N GroupDifferences between M16C/6NA and M16C/6N4REJ05B0466-0100Z/Rev.1.00 May 2004 Page 2 of 6Table 3.1.2 Function differences (mask ROM version

Seite 3

M16C/6N GroupDifferences between M16C/6NA and M16C/6N4REJ05B0466-0100Z/Rev.1.00 May 2004 Page 3 of 6Table 3.1.3 Function differences (flash memory ver

Seite 4

M16C/6N GroupDifferences between M16C/6NA and M16C/6N4REJ05B0466-0100Z/Rev.1.00 May 2004 Page 4 of 64. Website and Contact Information for Technical

Seite 5 - DEVISION HISTORY

M16C/6N GroupDifferences between M16C/6NA and M16C/6N4REJ05B0466-0100Z/Rev.1.00 May 2004 Page 5 of 6DEVISION HISTORYM16C/6N GroupDifferences between M

Seite 6

M16C/6N GroupDifferences between M16C/6NA and M16C/6N4REJ05B0466-0100Z/Rev.1.00 May 2004 Page 6 of 61. These materials are intended as a reference to

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