Renesas Emulator System M3T-MR100 Bedienungsanleitung PDF herunterladen (Seite 15)

REJ05B1160-0101 Rev.1.01 February 2010 Page 15 of 43

M16C/62P Group, R32C/111 Group

Differences between M16C/62P and R32C/111 (100 pin ver.)

4.7 Bus

Table 4.18 to Table 4.22 respectively list the changes on bus characteristics, settings, bus control pins,

and associated SFRs.

Table 4.18 Comparison Chart: Bus Characteristics

Item M16C/62P R32C/111

Address space 1 Mbyte/4 Mbytes (refer to memory

expansion function)

4 Gbytes

(available up to 64 Mbytes)

Address bus width 12/16/20 bits 24 bits fixed

External space wait states 1 to 3 wait states based on BCLK cycle 1 to 28 wait states based on base clock

cycle

Recovery cycle insert

(Address hold time after

read/write)

N/A Available

SFR area wait states 1 or 2 wait states (when PLL is in

operation)

No wait state,

Settable by the CCR register

(divide-by-1, 2, 3, or 4)

Table 4.19 Comparison Chart: Bus Settings

Item M16C/62P R32C/111

Address bus width • PM06 bit in the PM0 register

• PM11 bit in the PM1 register

N/A

Data bus width • All external space bus width is set by

the BYTE pin;

H: 8 bits

L: 16 bits

• Each external space bus width is set

by the BW0 bit in registers EBC0 to

EBC3;

0: 8 bits as width

1: 16 bits as width

• Maximum width of each external

space bus is set by the EXBW0 bit in

the PBC register;

0: 8 bits as maximum width

1: 16 bits as maximum width

• Bus width after a reset is set by the

lower two bits of reset vector

(applicable to external space CS0

only);

11b: 8 bits

10b: 16 bits

Chip select signals CSi bit in the CSR register (i = 0 to 3) Registers CSOP0 and CSOP1

SFR area bus timing PM20 bit in the PM2 register PBC register

External space bus timing • CSiW bit in the CSR register (i = 0 to

• Bits CSEi0 and CSEi1 in the CSE

EBCi register (i = 0 to 3)

BCLK output PM07 bit in the PM0 register • PM07 bit in the PM0 register

• Bits CM00 and CM01 in the CM0

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 42 43

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