Renesas Asynchronous SH7145F Bedienungsanleitung Seite 8

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SH7145 Group
SCI Break Detection
REJ06B0384-0100Z/Rev.1.00 September 2004 Page 8 of 20
Table 6 Description of Internal Registers (2)
Register
Name Bit Bit Name Setting Function
H'00 Serial mode register_0
Selects communication format and clock source for the
internal baud rate generator.
7 C/A 0 Communication mode
When C/A = 0, SCI0 operates in asynchronous mode.
6 CHR 0 Character length (only valid in asynchronous mode)
When CHR = 0, communication data length is 8 bits.
5 PE 0 Parity enable (only valid in asynchronous mode)
When PE= 0, communication is performed with no
parity.
4 O/E 0 Parity mode (valid when PE = 1 in asynchronous mode)
In this sample task, PE = 0 and so this bit is invalid.
3 STOP 0 Stop bit length (only valid in asynchronous mode)
When STOP = 0, one stop bit is used.
2 MP 0
Multiprocessor mode (only valid in asynchronous mode)
When MP = 0, multiprocessor communication function is
disabled.
SMR_0
1
0
CKS1
CKS0
0
0
Clock select 1, 0
When CKS1 = CKS0 = 0, the clock source for the
internal baud rate generator is set to Pφ.
BRR_0 H'40 Bit rate register_0
An 8-bit register used to adjust the bit rate.
SDCR_0 H'F2 Serial direction control register_0
The DIR bit (bit 3) is used to select LSB/MSB-first; in this
sample task, set to DIR = 0 (LSB-first).
H'xx Serial status register_0
Consists of SCI0 status flags and communication
multiprocessor bits; only 0 can be written to the status
flags for flag clearing.
7 TDRE * Transmit data register empty (status flag)
6 RDRF * Receive data register full (status flag)
5 ORER * Overrun error (status flag)
4 FER * Framing error (status flag)
3 PER * Parity error (status flag)
2 TEND * Transmit end (status flag)
1 MPB 0 Multiprocessor bit
SSR_0
0 MPBT 0 Multiprocessor bit transfer
Port A control register L2 PACRL2
0 PA0MD 1 PA0 mode bit
Specifies the function of PA0, a multiplexed pin of Port A
(RxD0).
Note: * Only clearing is possible; setting to 1 is done by hardware.
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