Renesas PROM Programming Adapter PCA7435FPG02 Spezifikationen PDF herunterladen (Seite 31)

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Rev.3.00 Oct 23, 2006 page 31 of 53

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Serial I/O2 operation

By writing to the serial I/O2 register(address 003116) the serial I/O2

counter is set to “7”.

After writing, the S

DATA pin outputs data every time the transfer clock

shifts from a high to a low level. And, as the transfer clock shifts from

a low to a high, the S

DATA pin reads data, and at the same time the

contents of the serial I/O2 register are shifted by 1 bit.

When the internal clock is selected as the transfer clock source, the

following operations execute as the transfer clock counts up to 8.

• Serial I/O2 counter is cleared to “0”.

• Transfer clock stops at an “H” level.

• Interrupt request bit is set.

• Shift completion flag is set.

Also, the SDATA pin is in a high impedance state after the data trans-

fer is complete. Refer to Figure 34.

When the external clock is selected as the transfer clock source, the

interrupt request bit is set as the transfer clock counts up to 8, but

external control of the clock is required since it does not stop. Notice

that the SDATA pin is not in a high impedance state on the completion

of data transfer.

Fig. 34 Serial I/O2 timing (LSB first)

Note : When the internal clock is selected as the transfer and the direction register of P1

DATA

pin is set to the input mode,

Synchronous clock

Serial I/O2 register

write signal

Transfer clock

(Note)

DATA

at serial I/O2

input receive

DATA

at serial I/O2

output transmit

Serial I/O2 interrupt request bit set

the S

DATA

pin is in a high impedance state after the data transfer is completed.

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