Renesas H8S/2128 Series Bedienungsanleitung

Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.The semiconductor operati

2• Wait function in slave mode (I2C bus format)A wait request can be generated by driving the SCL pin low after data transfer, excludingacknowledgeme

9222.2.5 Flash Memory CharacteristicsTable 22.13 shows the flash memory characteristics.Table 22.13 Flash Memory CharacteristicsConditions (5 V versio

93Item Symbol Min Typ Max UnitTestConditionErase Wait time afterSWE-bit setting*1x 10——µsWait time afterESU-bit setting*1y 200 — — µsWait time afterE-

9422.2.6 Usage NoteThe F-ZTAT and mask ROM versions have been confirmed as fully meeting the reference valuesfor electrical characteristics shown in t

9522.3 Electrical Characteristics [H8S/2128S Series]22.3.1 Absolute Maximum RatingsTable 22.14 lists the absolute maximum ratings.Table 22.14 Absolute

9622.3.2 DC CharacteristicsTable 22.15 lists the DC characteristics. Table 22.16 lists the permissible output currents.Table 22.15 DC Characteristics

97Item Symbol Min Typ Max Unit Test ConditionsThree-stateleakagecurrent(off state)Ports 1 to 6 ITSI — — 1.0 µA Vin = 0.5 toVCC – 0.5 VInputpull-upMO

98*5 The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is notselected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CI

99Table 22.15 DC Characteristics (2)Conditions: VCC = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, VSS = AVSS*1 = 0 V,Ta = –20 to +75°C (regular specifica

100Item Symbol Min Typ Max Unit Test ConditionsInput RES Iin — — 10.0 µA Vin = 0.5 toleakagecurrentSTBY, NMI, MD1,MD0— — 1.0 µAVCC – 0.5 VPort 7 — —

101An external pull-up resistor is necessary to provide high-level output from SCL0 andSDA0 (ICE = 1).In the H8S/2128S Series, P52/SCK0 and P47 (ICE =

3øPSNoisecancelerNoisecancelerClockcontrolFormatless dedicatedclock (channel 0 only)Bus statedecisioncircuitArbitrationdecisioncircuitOutput datacontr

102Table 22.15 DC Characteristics (3)Conditions (Mask ROM version): VCC = 2.7 V to 3.6 V, AVCC*1 = 2.7 V to 3.6 V,VSS = AVSS*1 = 0 V, Ta = –20 to +75°

103Item Symbol Min Typ Max Unit Test ConditionsThree-stateleakagecurrent(off state)Ports 1 to 6 ITSI — — 1.0 µA Vin = 0.5 toVCC – 0.5 VInputpull-upM

104*5 The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is notselected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when C

105Table 22.16 Permissible Output CurrentsConditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular specifications),Ta = –40 to +85°C (w

106Table 22.17 Bus Drive CharacteristicsConditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 to 3.6 V (3 V version), VSS = 0 VApplicable Pins: SCL1, SCL0, SDA

107600 ΩThis chipPorts 1 to 3LEDFigure 22.26 LED Drive Circuit (Example)22.3.3 AC CharacteristicsFigure 22.3 shows the test conditions for the AC ch

108(1) Clock TimingTable 22.18 shows the clock timing. The clock timing specified here covers clock (ø) output andclock pulse generator (crystal) and

109tCHtcyctCftCLtCrøFigure 22.28 System Clock TimingtOSC1tOSC1EXTALVCCSTBYRESøtDEXTtDEXTFigure 22.29 Oscillation Settling TimingøNMIIRQi(i = 0, 1

110(2) Control Signal TimingTable 22.19 shows the control signal timing. The only external interrupts that can operate on thesubclock (ø = 32.768 kHz

111tRESWtRESSøtRESSRESFigure 22.31 Reset Input TimingtIRQSøtNMIStNMIHIRQEdge inputNMI tIRQStIRQHIRQi(i = 2 to 0)IRQLevel inputtNMIWtIRQWFigure 22.32

4SCL inSCL outSDA inSDA out(Slave 1)SCLSDASCL inSCL outSDA inSDA out(Slave 2)SCLSDASCL inSCL outSDA inSDA out(Master)This chipSCLSDAVccVCCSCLSDAFigure

112(3) Bus TimingTable 22.20 shows the bus timing. Operation in external expansion mode is not guaranteed whenoperating on the subclock (ø = 32.768 k

113Condition A Condition B Condition C20 MHz 16 MHz 10 MHzTestItem Symbol Min Max Min Max Min Max Unit ConditionsRead dataaccess time 3tACC3— 2.0 ×tcy

114tRSD2øT1tADAS*A15 to A0, IOS*Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.tASDRD(read)tCSDT2tAStAStAStAS

115tRSD2øT2AS*A15 to A0, IOS*tASDRD(read)T3tAStAStAHtAHtASDtACC4tRSD1tACC5tRDStRDHtWRD1tWRD2tWDStWSW2tWDHD7 to D0(read)WR(write)D7 to D0(write)T1tWDD

116øTWAS*A15 to A0, IOS*RD(read)T3D7 to D0(read)WR(write)D7 to D0(write)T2tWTST1tWTHtWTStWTHWAITNote: * AS and IOS are the same pin. The function is

117tRSD2øT1AS*A15 to A0, IOS*T2tAHtACC3tRDSD7 to D0(read)T2 or T3 tAST1tASDtASDtRDHtADRD(read)Note: * AS and IOS are the same pin. The function is se

118tRSD2øT1AS*A15 to A0, IOS*T1tACC1D7 to D0(read)T2 or T3 tRDHtADRD(read)tRDSNote: * AS and IOS are the same pin. The function is selected by the IO

119(4) Timing of On-Chip Supporting ModulesTables 22.21 and 22.22 show the on-chip supporting module timing. The only on-chip supportingmodules that

120Condition A Condition B Condition C20 MHz 16 MHz 10 MHzTestItem Symbol Min Max Min Max Min Max Unit ConditionsTMR Timer outputdelay timetTMOD— 50 —

121øPorts 1 to 7 (read)T2T1tPWDtPRHtPRSPorts 1 to 6(write)Figure 22.38 I/O Port Input/Output TimingøtFTIStFTODFTOA, FTOBFTIA, FTIB,FTIC, FTIDFigure

516.1.4 Register ConfigurationTable 16.2 summarizes the registers of the I2C bus interface.Table 16.2 Register ConfigurationChannel Name Abbreviation

122øTMO0, TMO1TMOXtTMODFigure 22.41 8-Bit Timer Output TimingøTMCI0, TMCI1TMIX, TMIYtTMCStTMCStTMCWHtTMCWLFigure 22.42 8-Bit Timer Clock Input Tim

123SCK0, SCK1tSCKWtSCKrtSCKftScycFigure 22.45 SCK Clock Input TimingTxD0, TxD1(transmit data)RxD0, RxD1(receive data)SCK0, SCK1tRXStRXHtTXDFigure 22

124Table 22.22 I2C Bus TimingConditions: VCC = 4.0 V to 5.5 V, VCC = 2.7 V to 3.6 V (3 V version), VSS = 0 V, ø = 5 MHz tomaximum operating frequency,

125SDA0,SDA1VILVIHtBUFP* P*S*tSTAHtSCLHtSrtSCLLtSCLtSftSDAHSr*tSDAStSTAStSPtSTOSNote: * S, P, and Sr indicate the following conditions.S:P: Sr: Start

12622.3.4 A/D Conversion CharacteristicsTables 22.23 and 22.24 list the A/D conversion characteristics.Table 22.23 A/D Conversion Characteristics(AN7

127Table 22.24 A/D Conversion Characteristics(CIN7 to CIN0 Input: 134/266-State Conversion)Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%VSS = AVS

12822.3.5 Usage Note(1) The F-ZTAT and mask ROM versions have been confirmed as fully meeting the referencevalues for electrical characteristics shown

129(3) Specification differences in internal I/O registersMask ROM version of H8S/2128S, H8S/2127S are different from the H8S/2128 Series andH8S/2124

13022.4 Electrical Characteristics [H8S/2124 Series]22.4.1 Absolute Maximum RatingsTable 22.25 lists the absolute maximum ratings.Table 22.25 Absolute

13122.4.2 DC CharacteristicsTable 22.26 lists the DC characteristics. Table 22.27 lists the permissible output currents.Table 22.26 DC Characteristics

616.2 Register Descriptions16.2.1 I2C Bus Data Register (ICDR)BitInitial valueRead/Write7ICDR7—R/W6ICDR6—R/W5ICDR5—R/W4ICDR4—R/W3ICDR3—R/W0ICDR0—R/W2I

132Item Symbol Min Typ Max Unit Test ConditionsThree-stateleakagecurrent(off state)Ports 1 to 6 ITSI — — 1.0 µA Vin = 0.5 toVCC – 0.5 VInputpull-upM

133Table 22.26 DC Characteristics (2)Conditions: VCC = 4.0 V to 5.5 V, AVCC*1 = 4.0 V to 5.5 V, VSS = AVSS*1 = 0 V,Ta = –20 to +75°C (regular specific

134Item Symbol Min Typ Max Unit Test ConditionsThree-stateleakagecurrent(off state)Ports 1 to 6 ITSI — — 1.0 µA Vin = 0.5 toVCC – 0.5 VInputpull-upM

135Table 22.26 DC Characteristics (3)Conditions : VCC = 2.7 V to 5.5 V, AVCC*1 = 2.7 V to 5.5 V,VSS = AVSS*1 = 0 V, Ta = –20 to +75°CItem Symbol Min T

136Item Symbol Min Typ Max Unit Test ConditionsThree-stateleakagecurrent(off state)Ports 1 to 6 ITSI — — 1.0 µA Vin = 0.5 toVCC – 0.5 VInputpull-upM

137Table 22.27 Permissible Output CurrentsConditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular specifications),Ta = –40 to +85°C (w

1382 kΩThis chipPortDarlington pairFigure 22.50 Darlington Pair Drive Circuit (Example)600 ΩThis chipPorts 1 to 3LEDFigure 22.51 LED Drive Circuit

139(1) Clock TimingTable 22.28 shows the clock timing. The clock timing specified here covers clock (ø) output andclock pulse generator (crystal) and

140tCHtcyctCftCLtCrøFigure 22.53 System Clock TimingtOSC1tOSC1EXTALVCCSTBYRESøtDEXTtDEXTFigure 22.54 Oscillation Settling TimingøNMIIRQi(i = 0, 1

141(2) Control Signal TimingTable 22.29 shows the control signal timing. The only external interrupts that can operate on thesubclock (ø = 32.768 kHz

7ICDR is an 8-bit readable/writable register that is used as a transmit data register whentransmitting and a receive data register when receiving. ICD

142tRESWtRESSøtRESSRESFigure 22.56 Reset Input TimingtIRQSøtNMIStNMIHIRQEdge inputNMI tIRQStIRQHIRQi(i = 2 to 0)IRQLevel inputtNMIWtIRQWFigure 22.57

143(3) Bus TimingTable 22.30 shows the bus timing. Operation in external expansion mode is not guaranteed whenoperating on the subclock (ø = 32.768 k

144Condition A Condition B Condition C20 MHz 16 MHz 10 MHzTestItem Symbol Min Max Min Max Min Max Unit ConditionsRead dataaccess time 3tACC3— 2.0 ×tcy

145tRSD2øT1tADAS*A15 to A0, IOS*Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.tASDRD(read)tCSDT2tAStAStAStAS

146tRSD2øT2AS*A15 to A0, IOS*tASDRD(read)T3tAStAStAHtAHtASDtACC4tRSD1tACC5tRDStRDHtWRD1tWRD2tWDStWSW2tWDHD7 to D0(read)WR(write)D7 to D0(write)T1tWDD

147øTWAS*A15 to A0, IOS*RD(read)T3D7 to D0(read)WR(write)D7 to D0(write)T2tWTST1tWTHtWTStWTHWAITNote: * AS and IOS are the same pin. The function is

148tRSD2øT1AS*A15 to A0, IOS*T2tAHtACC3tRDSD7 to D0(read)T2 or T3 tAST1tASDtASDtRDHtADRD(read)Note: * AS and IOS are the same pin. The function is se

149tRSD2øT1AS*A15 to A0, IOS*T1tACC1D7 to D0(read)T2 or T3 tRDHtADRD(read)tRDSNote: * AS and IOS are the same pin. The function is selected by the IO

150(4) Timing of On-Chip Supporting ModulesTable 22.31 shows the on-chip supporting module timing. The only on-chip supporting modulesthat can operat

151Condition A Condition B Condition C20 MHz 16 MHz 10 MHzTestItem Symbol Min Max Min Max Min Max Unit ConditionsTMR Timer outputdelay timetTMOD— 50 —

8TDRE Description0 The next transmit data is in ICDR (ICDRT), or transmission cannot (Initial value)be started[Clearing conditions]• When transmit d

152øPorts 1 to 7 (read)T2T1tPWDtPRHtPRSPorts 1 to 6(write)Figure 22.63 I/O Port Input/Output TimingøtFTIStFTODFTOA, FTOBFTIA, FTIB,FTIC, FTIDFigure

153øTMO0, TMO1tTMODFigure 22.66 8-Bit Timer Output TimingøTMCI0, TMCI1, TMIYtTMCStTMCStTMCWHtTMCWLFigure 22.67 8-Bit Timer Clock Input TimingøTMRI

154TxD0, TxD1(transmit data)RxD0, RxD1(receive data)SCK0, SCK1tRXStRXHtTXDFigure 22.70 SCI Input/Output Timing (Synchronous Mode)øADTRGtTRGSFigure 2

15522.4.4 A/D Conversion CharacteristicsTables 22.32 and 22.33 list the A/D conversion characteristics.Table 22.32 A/D Conversion Characteristics(AN7

156Table 22.33 A/D Conversion Characteristics(CIN7 to CIN0 Input: 134/266-State Conversion)Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%VSS = AVS

15722.4.5 Usage NoteThe specifications of the H8S/2128 F-ZTAT version and H8S/2124 Series mask ROM versiondiffer in terms of on-chip module functions

158

159Appendix F Product Code LineupTable F.1 H8S/2128 Series and H8S/2124 Series Product Code Lineup — Preliminary —Product TypeProductCode Mark Co

160Product TypeProductCode Mark CodePackage(HitachiPackageCode) NotesH8S/2128SSeriesH8S/2128S Mask ROMversionStandard product(5 V version,HD6432128S H

161Product TypeProductCode Mark CodePackage(HitachiPackageCode) NotesH8S/2124SeriesH8S/2122 Mask ROMversionStandard product(5 V version,HD6432122 HD64

916.2.2 Slave Address Register (SAR)BitInitial valueRead/Write7SVA60R/W6SVA50R/W5SVA40R/W4SVA30R/W3SVA20R/W0FS0R/W2SVA10R/W1SVA00R/WSAR is an 8-bit re

162

H8S/2128 Series, H8S/2124 Series, H8S/2128F-ZTAT™Hardware Manual (Supplement)Publication Date: 1st Edition, December 19973rd Edition, May 2002Publish

10DDCSWRBit 6SARBit 0SARXBit 0SW FS FSX Operating Mode000 I2C bus format• SAR and SARX slave addresses recognized1I2C bus format• SAR slave address

11Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit inDDCSWR to select the communication format.• I2C bus format: addr

Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products bett

12Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of dataand the acknowledge bit, in master mode with the I2C b

13Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel1) or IICX0 (channel 0) bit in the STCR register, select

14Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to betransferred next. With the I2C bus format (when the FS bit in

15Bit 7—I2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to beused. When ICE is set to 1, port pins function as SCL and

16Bit 5 Bit 4MST TRS Operating Mode0 0 Slave receive mode (Initial value)1 Slave transmit mode1 0 Master receive mode1 Master transmit modeBit 5MST De

17Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of theacknowledge bit returned from the receiving device when using th

18Bit 2BBSY Description0 Bus is free[Clearing condition]When a stop condition is detected(Initial value)1 Bus is busy[Setting condition]When a start c

19Bit 1IRIC Description0 Waiting for transfer, or transfer in progress (Initial value)[Clearing conditions]1. When 0 is written in IRIC after reading

20When, with the I2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flagsmust be checked in order to identify the source t

21Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stopconditions in master mode. To issue a start condition, wr

Hitachi 16-Bit Single-Chip MicrocomputerH8S/2128 Series, H8S/2124 SeriesH8S/2128F-ZTAT™Hardware Manual— Supplement —ADE-602-114BRev. 3.05/22/02Hitachi

22Bit 7ESTP Description0 No error stop condition[Clearing conditions]1. When 0 is written in ESTP after reading ESTP = 12. When the IRIC flag is clear

23Bit 5IRTR Description0 Waiting for transfer, or transfer in progress[Clearing conditions]1. When 0 is written in IRTR after reading IRTR = 12. When

24AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL isreset automatically by write access to ICDR in trans

25Bit 1—General Call Address Recognition Flag (ADZ): In I2C bus format slave receive mode,this flag is set to 1 if the first frame following a start c

2616.2.7 Serial/Timer Control Register (STCR)BitInitial valueRead/Write7—0R/W6IICX10R/W5IICX00R/W4IICE0R/W3FLSHE0R/W0ICKS00R/W2—0R/W1ICKS10R/WSTCR is

2716.2.8 DDC Switch Register (DDCSWR)BitInitial valueRead/WriteNotes: *1 Only 0 can be written, to clear the flag.*2 Always read as 1.7SWE0R/W6SW0R/W5

28Bits 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt requestto the CPU when automatic format switching is executed for

29Bit 3 Bit 2 Bit 1 Bit 0CLR3 CLR2 CLR1 CLR0 Description0 0 — — Setting prohibited1 0 0 Setting prohibited1 IIC0 internal latch cleared1 0 IIC1 intern

30MSTPCRL Bit 3—Module Stop (MSTP3): Specifies IIC channel 1 module stop mode.MSTPCRLBit 3MSTP3 Description0 IIC channel 1 module stop mode is cleared

31S SLA R/W A DATA A A/A P1111n71 m(a) I2C bus format (FS = 0 or FSX = 0)(b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0)n: t

Cautions1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’spatent, copyright, trademark, or other intellec

32Table 16.4 I2C Bus Data Format SymbolsLegendS Start condition. The master device drives SDA from high to low while SCL is highSLA Slave address, by

33The master device sequentially sends the transmit clock and the data written to ICDR with thetiming shown in figure 16.7. The selected slave device

34SDA(master output)SDA(slave output)21R/W436587129Abit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0bit 7 bit 6IRICIRTRICDRSCL(master output)Start cond

35(3) The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At thispoint, if the IEIC bit of ICCR is set to 1, an int

369A Bit7Master receive modeMaster transmit modeSCL(master output)SDA(slave output)SDA(master output)IRICIRTRICDRUser processing [1] TRS cleared to 0W

3716.3.4 Slave Receive OperationIn slave receive mode, the master device outputs the transmit clock and transmit data, and theslave device returns an

38SDA(master output)SDA(slave output)21 214365879Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0IRICICDRSICDRRRDRFSCL(master output)Start c

39SDA(master output)SDA(slave output)214365879879Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Bit 1 Bit 0IRICICDRSICDRRRDRFSCL(master output)SCL(sla

40flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. Theslave device sequentially sends the data written into I

4116.3.6 IRIC Setting Timing and SCL ControlThe interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, theFS bit i

February 2002Announcement of Changes to Hardware Manual ContentsThis is to announce that, with the addition of H8S/2128S and H8S/2127S products, a Sup

4216.3.7 Automatic Switching from Formatless Mode to I2C Bus FormatSetting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC

4316.3.8 Operation Using the DTCThe I2C bus format provides for selection of the slave device and transfer direction by means ofthe slave address and

4416.3.9 Noise CancelerThe logic levels at the SCL and SDA pins are routed through noise cancelers before being latchedinternally. Figure 16.13 shows

45StartInitializeRead BBSY in ICCRNoBBSY = 0?YesYesSet MST = 1 andTRS = 1 in ICCRWrite BBSY = 1and SCP = 0 in ICCRClear IRIC in ICCRRead IRIC in ICCRN

46Master receive operationRead ICDRClear IRIC in ICCRIRIC = 1?Clear IRIC in ICCRRead IRIC in ICCRIRIC = 1?Last receive ?YesYesNoNoNoYesYesYesNoYesRead

47StartInitializeSet MST = 0and TRS = 0 in ICCRSet ACKB = 0 in ICSRRead IRIC in ICCRIRIC = 1?YesNoClear IRIC in ICCRRead AAS and ADZ in ICSRAAS = 1and

48Slave transmit modeWrite transmit data in ICDRRead IRIC in ICCRIRIC = 1?Clear IRIC in ICCRClear IRIC in ICCRClear IRIC in ICCRRead ACKB in ICSRSet T

49• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, dataoutput, etc.)The following items are not initialized:•

5016.4 Usage Notes• In master mode, if an instruction to generate a start condition is immediately followed by aninstruction to generate a stop condi

51• The I2C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high-speed mode). In master mode, the I2C bus interfac

52Table 16.8 I2C Bus Timing (with Maximum Influence of tSr/tSf)Time Indication (at Maximum Transfer Rate) [ns]ItemtcycIndicationtSr/tSfInfluence(Max.)

53Time Indication (at Maximum Transfer Rate) [ns]ItemtcycIndicationtSr/tSfInfluence(Max.)I2C BusSpecifi-cation(Min.)ø =5 MHzø =8 MHzø =10 MHzø =16 MHz

54SDASCLInternal clockBBSY bitMaster receive modeICDR readingprohibitedBit 0A89Stop condition(a)Start conditionExecution of stop condition issuance in

55Read SCL pinWrite transmit data to ICDRClear IRIC in ICSRWrite BBSY = 1,SCP = 0 (ICSR)IRIC= 1 ?NoSCL= Low ?NoYesStart conditionissuance?No[1][2][3][

56• Notes on I2C Bus Interface Stop Condition Instruction IssuanceIf the rise time of the 9th SCL clock exceeds the specification because the bus loa

57Section 22 Electrical Characteristics22.1 Voltage of Power Supply and Operating RangeThe power supply voltage and operating range (shaded part) fo

58Table 22.1 Power Supply Voltage and Operating Range (2) (Mask ROM Products)Product/Power supply 5 V version 4 V version 3 V versionHD6432128SHD64321

5922.2 Electrical Characteristics [H8S/2128 Series, H8S/2128 F-ZTAT]22.2.1 Absolute Maximum RatingsTable 22.2 lists the absolute maximum ratings.Table

6022.2.2 DC CharacteristicsTable 22.3 lists the DC characteristics. Table 22.4 lists the permissible output currents.Table 22.3 DC Characteristics (1)

61Item Symbol Min Typ Max Unit Test ConditionsThree-stateleakagecurrent(off state)Ports 1 to 6 ITSI — — 1.0 µA Vin = 0.5 toVCC – 0.5 VInputpull-upMO

iContentsSection 16 I2C Bus Interface [Option]... 116.1 Overview ...

62*5 The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is notselected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CI

63Table 22.3 DC Characteristics (2)Conditions: VCC = 4.0 V to 5.5 V*8, AVCC*1 = 4.0 V to 5.5 V, VSS = AVSS*1 = 0 V,Ta = –20 to +75°C*8 (regular specif

64Item Symbol Min Typ Max Unit Test ConditionsThree-stateleakagecurrent(off state)Ports 1 to 6 ITSI — — 1.0 µA Vin = 0.5 toVCC – 0.5 VInputpull-upMO

65*6 Current dissipation values are for VIH min = VCC – 0.5 V and VIL max = 0.5 V with alloutput pins unloaded and the on-chip pull-up MOSs in the off

66Table 22.3 DC Characteristics (3)Conditions (Mask ROM version): VCC = 2.7 V to 5.5 V, AVCC*1 = 2.7 V to 5.5 V,VSS = AVSS*1 = 0 V, Ta = –20 to +75°C(

67Item Symbol Min Typ Max Unit Test ConditionsThree-stateleakagecurrent(off state)Ports 1 to 6 ITSI — — 1.0 µA Vin = 0.5 toVCC – 0.5 VInputpull-upMO

68*5 The upper limit of the port 6 applied voltage is VCC + 0.3 V when CIN input is notselected, and the lower of VCC + 0.3 V and AVCC + 0.3 V when CI

69Table 22.4 Permissible Output CurrentsConditions: VCC = 4.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C (regular specifications),Ta = –40 to +85°C (wid

70Table 22.5 Bus Drive CharacteristicsConditions: VCC = 2.7 V to 5.5 V, VSS = 0 VApplicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected

71600 ΩThis chipPorts 1 to 3LEDFigure 22.2 LED Drive Circuit (Example)22.2.3 AC CharacteristicsFigure 22.3 shows the test conditions for the AC char

ii22.3 Electrical Characteristics [H8S/2128S Series] ... 9522.3.1 Absolute Maximum R

72(1) Clock TimingTable 22.6 shows the clock timing. The clock timing specified here covers clock (ø) output andclock pulse generator (crystal) and e

73tCHtcyctCftCLtCrøFigure 22.4 System Clock TimingtOSC1tOSC1EXTALVCCSTBYRESøtDEXTtDEXTFigure 22.5 Oscillation Settling TimingøNMIIRQi(i = 0, 1, 2

74(2) Control Signal TimingTable 22.7 shows the control signal timing. The only external interrupts that can operate on thesubclock (ø = 32.768 kHz)

75tRESWtRESSøtRESSRESFigure 22.7 Reset Input TimingtIRQSøtNMIStNMIHIRQEdge inputNMI tIRQStIRQHIRQi(i = 2 to 0)IRQLevel inputtNMIWtIRQWFigure 22.8

76(3) Bus TimingTable 22.8 shows the bus timing. Operation in external expansion mode is not guaranteed whenoperating on the subclock (ø = 32.768 kHz

77Condition A Condition B Condition C20 MHz 16 MHz 10 MHzTestItem Symbol Min Max Min Max Min Max Unit ConditionsRead dataaccess time 3tACC3— 2.0 ×tcyc

78tRSD2øT1tADAS*A15 to A0, IOS*Note: * AS and IOS are the same pin. The function is selected by the IOSE bit in SYSCR.tASDRD(read)tCSDT2tAStAStAStASD

79tRSD2øT2AS*A15 to A0, IOS*tASDRD(read)T3tAStAStAHtAHtASDtACC4tRSD1tACC5tRDStRDHtWRD1tWRD2tWDStWSW2tWDHD7 to D0(read)WR(write)D7 to D0(write)T1tWDDt

80øTWAS*A15 to A0, IOS*RD(read)T3D7 to D0(read)WR(write)D7 to D0(write)T2tWTST1tWTHtWTStWTHWAITNote: * AS and IOS are the same pin. The function is

81tRSD2øT1AS*A15 to A0, IOS*T2tAHtACC3tRDSD7 to D0(read)T2 or T3 tAST1tASDtASDtRDHtADRD(read)Note: * AS and IOS are the same pin. The function is sel

1Section 16 I2C Bus Interface [Option]A two-channel I2C bus interface is available as an option in the H8S/2128 Series. The I2C businterface is not

82tRSD2øT1AS*A15 to A0, IOS*T1tACC1D7 to D0(read)T2 or T3 tRDHtADRD(read)tRDSNote: * AS and IOS are the same pin. The function is selected by the IOS

83(4) Timing of On-Chip Supporting ModulesTables 22.9 and 22.10 show the on-chip supporting module timing. The only on-chip supportingmodules that ca

84Condition A Condition B Condition C20 MHz 16 MHz 10 MHzTestItem Symbol Min Max Min Max Min Max Unit ConditionsTMR Timer outputdelay timetTMOD— 50 —

85øPorts 1 to 7 (read)T2T1tPWDtPRHtPRSPorts 1 to 6(write)Figure 22.14 I/O Port Input/Output TimingøtFTIStFTODFTOA, FTOBFTIA, FTIB,FTIC, FTIDFigure 2

86øTMO0, TMO1TMOXtTMODFigure 22.17 8-Bit Timer Output TimingøTMCI0, TMCI1TMIX, TMIYtTMCStTMCStTMCWHtTMCWLFigure 22.18 8-Bit Timer Clock Input Timi

87SCK0, SCK1tSCKWtSCKrtSCKftScycFigure 22.21 SCK Clock Input TimingTxD0, TxD1(transmit data)RxD0, RxD1(receive data)SCK0, SCK1tRXStRXHtTXDFigure 22.

88Table 22.10 I2C Bus TimingConditions: VCC = 2.7 V to 5.5 V, VSS = 0 V, ø = 5 MHz to maximum operating frequency,Ta = –20 to +75°CItem Symbol Min Typ

89SDA0,SDA1VILVIHtBUFP* P*S*tSTAHtSCLHtSrtSCLLtSCLtSftSDAHSr*tSDAStSTAStSPtSTOSNote: * S, P, and Sr indicate the following conditions.S:P: Sr: Start

9022.2.4 A/D Conversion CharacteristicsTables 22.11 and 22.12 list the A/D conversion characteristics.Table 22.11 A/D Conversion Characteristics(AN7 t

91Table 22.12 A/D Conversion Characteristics(CIN7 to CIN0 Input: 134/266-State Conversion)Condition A: VCC = 5.0 V ± 10%, AVCC = 5.0 V ± 10%VSS = AVSS